1. Field of the Invention
The invention relates generally to serial selection circuits for semiconductor memories, and more particularly, to a serial selection circuit having simplified circuit structures. The invention has particular applicability to first-in first-out (FIFO) memories.
2. Description of the Background Art
In a semiconductor memory, there is often a need for accessing a memory cell for storing data in a predetermined sequence. That is, in a first-in first-out (hereinafter referred to as FIFO) memory having FIFO function, a last-in first-out (hereinafter referred to as LIFO) memory having LIFO function, a serial input-parallel output memory, a parallel input-serial output memory, a parallel input-parallel output memory and serial input-serial output memory and so on, it is necessary to designate a memory cell to be accessed in accordance with a predetermined sequence. The present invention is applicable to a serial selection circuit capable of selecting a memory cell row (or column) to be accessed in accordance with a predetermined sequence. A serial selection in a FIFO memory will be described in the following, as an example.
In a FIFO memory, stored data is read from a memory cell in the order that the data was written. That is, the stored data is read in a sequential order from the oldest one. In the case in which data is transmitted between devices or circuits having different processing speeds, a FIFO memory is often utilized in order to temporarily hold the data, and then adjust the timing.
FIG. 5 is a block diagram of a conventional FIFO memory. Referring to FIG. 5, this FIFO memory 2 includes 4096 static type memory cells MC disposed in a matrix including 1024 rows. Each 4 memory cells MC are respectively connected to a row decoder 17 over word lines W0 to W1023. 4 bit line pairs constituting 4 columns are connected to an I/O line pair 3 over a column selector 6.
This FIFO memory 2 includes a 2-bit counter 4 and a 10-bit counter 16 driven by an externally applied clock signal .phi.. The input terminals of the decoder 5 for decoding a 2-bit signal are connected to the output Q.sub.A of the counter 4. The decoder 5 is responsive to the signal Q.sub.A for generating selection signals S0 to S3 for selecting one of 4 bit line pairs.
The counter 4 generates a carry signal RCO representing a cycle of the counter operation, i.e., a carry of the counter, and then applies it to the 10-bit counter 16. The counter 16 is responsive to the clock signal .phi. when the carry signal RCO is applied for effecting the counter operation. The counter 16 generates counter signals of 10 bits I0 to I9 for selecting 1024 word lines, and applies them to the row decoder 17. The row decoder 17 decodes the signals I0 to I9, and selects one of the word lines W0 to W1023.
Connected to the I/0 line pair 3 are a write control circuit 11 for controlling the writing of data, and an output control circuit 13 for controlling data output. The output control circuit 13 includes an output buffer, and is connected to a data output terminal Do. The write control circuit 12 is connected to receive an externally applied write control signal WR and connected to a data input terminal Di.
FIG. 6 is a timing chart for describing the operation of the FIFO memory 2 shown in FIG. 5. Referring to FIGS. 5 and 6, the operation will be explained. The 2-bit counter 4 effects the counter operation, and generates a counter signal Q.sub.A of 2 bits in response to an externally applied clock signal .phi.. The decoder 5 generates signals S0 to S3 for selecting one of 4 bit line pairs in response to the signal Q.sub.A. That is, when the signal Q.sub.A generated from the counter 4 is (0).sub.H, only the signal S0 attains a high level. Accordingly, a memory cell connected to the bit line pair on the column "0" is selected. Similarly, when the signal Q.sub.A is (1).sub.H, only the signal S1 attains a high level. The column "1" is then selected. When the signal Q.sub.A is (2).sub.H, only the signal S2 attains a high level. The column "2" is selected. When the signal Q.sub.A is (3).sub.H, only the signal S3 attains a high level. The column "3" is therefore selected.
When 2-bit counter 4 applies the signal Q.sub.A of (3).sub.H, it generates a carry signal RCO at a high level. When the signal RCO is at a high level, the 10-bit counter 16 effects the count operation in response to the clock signal .phi.. The row decoder 17 drives high only one of the word lines W0 to W1023 in response to the output signals I0 to I9 of 10 bits applied from the counter. For example, the row decoder 17 drives only the word line W0 high in response to the output data I0 to I9 of (0).sub.H generated from the counter 16. As a result, the memory cell on the column "0" among 4 memory cells connected to the word line W0 is designated.
In the period in which the word line W0 is at a high level, other columns "1", "2" and "3" are sequentially selected. That is, the decoder 5 sequentially supplies the signals S1 to S3 at a high level in response to the signal Q.sub.A. Consequently, in the period in which the word line W0 is at a high level, that is, in the period in which the row "0" is selected, 4 memory cells on the row "0" are sequentially selected.
When the counter 4 supplies the carry signal RCO to the counter 16, the counter 16 applies to the row decoder 17 output data I0 to I9 for selecting the word line W1. The row decoder 17 drives only the word line W1 high. The column decoder 5 sequentially generates the output signals S0 to S3 at a high level in response to the signal Q.sub.A generated from the counter 4. Therefore, in the period in which the word line W1 is a high level, that is, in the period in which the row "1" is selected, 4 columns are sequentially selected.
It is becomes possible to access 4096 memory cells in a predetermined sequence by repeating the above-mentioned operation with respect to the all 1024 word lines W0 to W1023. The predetermined sequence is such that (row, column) to be accessed comes as follows: (0, 0), (0, 1), (0, 2), (0, 3), (1, 0), (1, 1), (1, 2), (1, 3), (2, 0), . . . (1023, 2), (1023, 3). That is, in write operation, the data supplied to the data input terminal Din is written into the memory cell MC in this sequence. In read operation, the data written into the memory cell MC is read-out through the data output terminal Do in this sequence.
FIG. 7 is a circuit diagram illustrating an example of the row decoder 17 shown in FIG. 5. Referring to FIG. 7, this row decoder 17 includes a multiplicity of NAND gates connected to receive the data I0 to I9 generated from the 10-bit counter 16 and the inverted data thereof. In operation, for example, when the 10-bit counter 16 generates the data (0).sub.H, only the word line W0 is driven high. When the counter 16 is incremented, and the data (1).sub.H is generated, then only the word line W1 is driven high. When the same operation is repeated and data (3FF).sub.H is generated, then only the word line W1023 is driven high. As a result, this row decoder 17 may sequentially drive all the word lines W0 to W1023 high.
As described above, the conventional FIFO memory 2 requires a multiplicity of NAND gates to constitute the row decoder 17. That means that the circuit for constituting the row decoder 17 becomes complicated, and that the occupied area of the circuit on the semiconductor chip is increased. In addition, the 2-bit counter 4 and the 10-bit counter 16 are also required, so that the area occupied by the circuit for making up these counters is increased.